Add batch 5 (Luthiraa_TALOS-V2, dawsonjon_fpu, The-OpenROAD-Project_OpenROAD-flow-scripts, antonblanchard_microwatt, alexforencich_verilog-i2c)
784ee2c verified | source $::env(SCRIPTS_DIR)/load.tcl | |
| erase_non_stage_variables final | |
| load_design 6_final.odb 6_final.sdc | |
| write_cdl -masters $::env(CDL_FILE) $::env(RESULTS_DIR)/6_final.cdl | |