| #initialize the design | |
| read_celllib -early optimizer_Early.lib | |
| read_celllib -late optimizer_Late.lib | |
| read_verilog optimizer.v | |
| read_spef optimizer.spef | |
| read_sdc optimizer.sdc | |
| # report the TNS and WNS | |
| report_tns | |
| report_wns | |
| # repower gate | |
| repower_gate inst_10 INV_X16 | |
| # insert a buffer to the design | |
| insert_gate TAUGATE_1 BUF_X2 | |
| insert_net TAUNET_1 | |
| disconnect_pin inst_3:ZN | |
| connect_pin inst_3:ZN TAUNET_1 | |
| connect_pin TAUGATE_1:A TAUNET_1 | |
| connect_pin TAUGATE_1:Z net_14 | |
| # updateh parasitics | |
| read_spef change_1.spef | |
| # automatically trigger incremental timing | |
| report_slack -pin G17 -late -fall | |
| report_at -pin G17 -late -fall | |
| report_rat -pin G17 -late -fall | |
| report_path -num_paths 1 | |
| # dump all slack values | |
| dump_slack | |