Download OpenROAD/src/cts/test/array_tile.lib from SAIFIINDUSTRIES/verilog_data-1: direct link, hf CLI and curl.
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4.17 kB
| library(array_tile) { | |
| technology (cmos); | |
| delay_model : table_lookup; | |
| revision : 1.0; | |
| date : "2021-12-02 00:16:14Z"; | |
| comment : "SRAM"; | |
| time_unit : "1ns"; | |
| voltage_unit : "1V"; | |
| current_unit : "1uA"; | |
| leakage_power_unit : "1nw"; | |
| nom_process : 1; | |
| nom_temperature : 25.000; | |
| nom_voltage : 1.1; | |
| capacitive_load_unit (1,ff); | |
| pulling_resistance_unit : "1kohm"; | |
| operating_conditions(tt_1.0_25.0) { | |
| process : 1; | |
| temperature : 25.000; | |
| voltage : 1.1; | |
| tree_type : balanced_tree; | |
| } | |
| /* default attributes */ | |
| default_cell_leakage_power : 0; | |
| default_fanout_load : 1; | |
| default_inout_pin_cap : 0.0; | |
| default_input_pin_cap : 0.0; | |
| default_output_pin_cap : 0.0; | |
| default_input_pin_cap : 0.0; | |
| default_max_transition : 0.227; | |
| default_operating_conditions : tt_1.0_25.0; | |
| default_leakage_power_density : 0.0; | |
| /* additional header data */ | |
| slew_derate_from_library : 1.000; | |
| slew_lower_threshold_pct_fall : 20.000; | |
| slew_upper_threshold_pct_fall : 80.000; | |
| slew_lower_threshold_pct_rise : 20.000; | |
| slew_upper_threshold_pct_rise : 80.000; | |
| input_threshold_pct_fall : 50.000; | |
| input_threshold_pct_rise : 50.000; | |
| output_threshold_pct_fall : 50.000; | |
| output_threshold_pct_rise : 50.000; | |
| lu_table_template(array_tile_out_slew_template) { | |
| variable_1 : total_output_net_capacitance; | |
| index_1 ("1000, 1001"); | |
| } | |
| library_features(report_delay_calculation); | |
| cell(array_tile) { | |
| interface_timing : true; | |
| pin(clk) { | |
| direction : input; | |
| clock : true; | |
| } | |
| pin(e_out) { | |
| direction : output; | |
| timing() { | |
| related_pin : "clk" ; | |
| timing_type : rising_edge; | |
| timing_sense : non_unate; | |
| cell_rise(scalar) { | |
| values ("0.213"); | |
| } | |
| cell_fall(scalar) { | |
| values ("0.213"); | |
| } | |
| rise_transition(array_tile_out_slew_template) { | |
| index_1 ("5.000, 500.000"); | |
| values ("0.009, 0.227") | |
| } | |
| fall_transition(array_tile_out_slew_template) { | |
| index_1 ("5.000, 500.000"); | |
| values ("0.009, 0.227") | |
| } | |
| } | |
| } | |
| pin(e_in){ | |
| direction : input; | |
| timing() { | |
| related_pin : clk; | |
| timing_type : setup_rising ; | |
| rise_constraint(scalar) { | |
| values ("0.050"); | |
| } | |
| fall_constraint(scalar) { | |
| values ("0.050"); | |
| } | |
| } | |
| timing() { | |
| related_pin : clk; | |
| timing_type : hold_rising ; | |
| rise_constraint(scalar) { | |
| values ("0.050"); | |
| } | |
| fall_constraint(scalar) { | |
| values ("0.050"); | |
| } | |
| } | |
| } | |
| pin(w_out) { | |
| direction : output; | |
| timing() { | |
| related_pin : "clk" ; | |
| timing_type : rising_edge; | |
| timing_sense : non_unate; | |
| cell_rise(scalar) { | |
| values ("0.213"); | |
| } | |
| cell_fall(scalar) { | |
| values ("0.213"); | |
| } | |
| rise_transition(array_tile_out_slew_template) { | |
| index_1 ("5.000, 500.000"); | |
| values ("0.009, 0.227") | |
| } | |
| fall_transition(array_tile_out_slew_template) { | |
| index_1 ("5.000, 500.000"); | |
| values ("0.009, 0.227") | |
| } | |
| } | |
| } | |
| pin(w_in){ | |
| direction : input; | |
| timing() { | |
| related_pin : clk; | |
| timing_type : setup_rising ; | |
| rise_constraint(scalar) { | |
| values ("0.050"); | |
| } | |
| fall_constraint(scalar) { | |
| values ("0.050"); | |
| } | |
| } | |
| timing() { | |
| related_pin : clk; | |
| timing_type : hold_rising ; | |
| rise_constraint(scalar) { | |
| values ("0.050"); | |
| } | |
| fall_constraint(scalar) { | |
| values ("0.050"); | |
| } | |
| } | |
| } | |
| } | |
| } | |