File size: 16,392 Bytes
23d354c | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 | --- get_cells with wildcard * ---
buf* cells: 1
--- get_cells with ? wildcard ---
buf? cells: 1
--- get_cells exact match ---
buf1 cells: 1
--- get_cells * ---
* cells: 3
--- get_pins with wildcards ---
buf1/* pins: 2
buf1/? pins: 2
*/* pins: 10
--- get_ports with wildcards ---
*1 ports: 2
* ports: 3
--- get_nets with wildcards ---
n* nets: 2
--- non-matching patterns ---
get_cells nonexistent count: 0
get_pins nonexistent count: 0
--- get_lib_cells with wildcards ---
BUF* lib_cells: 6
DFF_X? lib_cells: 2
* lib_cells: 134
--- set_debug with level > 0 ---
delay_calc: delays invalid
delay_calc: find delays to level 50
delay_calc: found 9 delays
search: find arrivals pass 1
search: find arrivals to level 50
search: find arrivals in1
search: arrival seed input arrival in1
search: find arrivals clk
search: arrival seed clk default/clk pin clk
search: find arrivals reg1/IQN
search: find arrivals reg1/IQ
search: find arrivals reg1/CK
search: clk
search: ^ -> ^ min
search: from tag: 4 default ^min clk ^ (clock ideal) clk_src clk crpr_pin null
search: to tag : 4 default ^min clk ^ (clock ideal) clk_src clk crpr_pin null
search: 0.000 + 0.000 = 0.000 < MIA
search: clk
search: ^ -> ^ max
search: from tag: 8 default ^max clk ^ (clock ideal) clk_src clk crpr_pin null
search: to tag : 8 default ^max clk ^ (clock ideal) clk_src clk crpr_pin null
search: 0.000 + 0.000 = 0.000 > MIA
search: clk
search: v -> v min
search: from tag: 7 default vmin clk v (clock ideal) clk_src clk crpr_pin null
search: to tag : 7 default vmin clk v (clock ideal) clk_src clk crpr_pin null
search: 5.000 + 0.000 = 5.000 < MIA
search: clk
search: v -> v max
search: from tag: 11 default vmax clk v (clock ideal) clk_src clk crpr_pin null
search: to tag : 11 default vmax clk v (clock ideal) clk_src clk crpr_pin null
search: 5.000 + 0.000 = 5.000 > MIA
search: find arrivals buf1/A
search: in1
search: ^ -> ^ min
search: from tag: 0 default ^min clk ^ clk_src clk crpr_pin null input in1
search: to tag : 12 default ^min clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.000 = 0.000 < MIA
search: in1
search: ^ -> ^ max
search: from tag: 2 default ^max clk ^ clk_src clk crpr_pin null input in1
search: to tag : 14 default ^max clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.000 = 0.000 > MIA
search: in1
search: v -> v min
search: from tag: 1 default vmin clk ^ clk_src clk crpr_pin null input in1
search: to tag : 13 default vmin clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.000 = 0.000 < MIA
search: in1
search: v -> v max
search: from tag: 3 default vmax clk ^ clk_src clk crpr_pin null input in1
search: to tag : 15 default vmax clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.000 = 0.000 > MIA
search: find arrivals buf1/Z
search: buf1/A
search: ^ -> ^ min
search: from tag: 12 default ^min clk ^ clk_src clk crpr_pin null
search: to tag : 12 default ^min clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.018 = 0.018 < MIA
search: buf1/A
search: ^ -> ^ max
search: from tag: 14 default ^max clk ^ clk_src clk crpr_pin null
search: to tag : 14 default ^max clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.018 = 0.018 > MIA
search: buf1/A
search: v -> v min
search: from tag: 13 default vmin clk ^ clk_src clk crpr_pin null
search: to tag : 13 default vmin clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.022 = 0.022 < MIA
search: buf1/A
search: v -> v max
search: from tag: 15 default vmax clk ^ clk_src clk crpr_pin null
search: to tag : 15 default vmax clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.022 = 0.022 > MIA
search: find arrivals reg1/Q
search: reg1/CK
search: ^ -> ^ min
search: from tag: 4 default ^min clk ^ (clock ideal) clk_src clk crpr_pin null
search: to tag : 12 default ^min clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.081 = 0.081 < MIA
search: reg1/CK
search: ^ -> v min
search: from tag: 4 default ^min clk ^ (clock ideal) clk_src clk crpr_pin null
search: to tag : 13 default vmin clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.075 = 0.075 < MIA
search: reg1/CK
search: ^ -> ^ max
search: from tag: 8 default ^max clk ^ (clock ideal) clk_src clk crpr_pin null
search: to tag : 14 default ^max clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.081 = 0.081 > MIA
search: reg1/CK
search: ^ -> v max
search: from tag: 8 default ^max clk ^ (clock ideal) clk_src clk crpr_pin null
search: to tag : 15 default vmax clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.075 = 0.075 > MIA
search: find arrivals reg1/QN
search: reg1/CK
search: ^ -> ^ min
search: from tag: 4 default ^min clk ^ (clock ideal) clk_src clk crpr_pin null
search: to tag : 12 default ^min clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.056 = 0.056 < MIA
search: reg1/CK
search: ^ -> v min
search: from tag: 4 default ^min clk ^ (clock ideal) clk_src clk crpr_pin null
search: to tag : 13 default vmin clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.057 = 0.057 < MIA
search: reg1/CK
search: ^ -> ^ max
search: from tag: 8 default ^max clk ^ (clock ideal) clk_src clk crpr_pin null
search: to tag : 14 default ^max clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.056 = 0.056 > MIA
search: reg1/CK
search: ^ -> v max
search: from tag: 8 default ^max clk ^ (clock ideal) clk_src clk crpr_pin null
search: to tag : 15 default vmax clk ^ clk_src clk crpr_pin null
search: 0.000 + 0.057 = 0.057 > MIA
search: find arrivals out1
search: reg1/Q
search: ^ -> ^ min
search: from tag: 12 default ^min clk ^ clk_src clk crpr_pin null
search: to tag : 12 default ^min clk ^ clk_src clk crpr_pin null
search: 0.081 + 0.000 = 0.081 < MIA
search: reg1/Q
search: ^ -> ^ max
search: from tag: 14 default ^max clk ^ clk_src clk crpr_pin null
search: to tag : 14 default ^max clk ^ clk_src clk crpr_pin null
search: 0.081 + 0.000 = 0.081 > MIA
search: reg1/Q
search: v -> v min
search: from tag: 13 default vmin clk ^ clk_src clk crpr_pin null
search: to tag : 13 default vmin clk ^ clk_src clk crpr_pin null
search: 0.075 + 0.000 = 0.075 < MIA
search: reg1/Q
search: v -> v max
search: from tag: 15 default vmax clk ^ clk_src clk crpr_pin null
search: to tag : 15 default vmax clk ^ clk_src clk crpr_pin null
search: 0.075 + 0.000 = 0.075 > MIA
search: find arrivals inv1/A
search: buf1/Z
search: ^ -> ^ min
search: from tag: 12 default ^min clk ^ clk_src clk crpr_pin null
search: to tag : 12 default ^min clk ^ clk_src clk crpr_pin null
search: 0.018 + 0.000 = 0.018 < MIA
search: buf1/Z
search: ^ -> ^ max
search: from tag: 14 default ^max clk ^ clk_src clk crpr_pin null
search: to tag : 14 default ^max clk ^ clk_src clk crpr_pin null
search: 0.018 + 0.000 = 0.018 > MIA
search: buf1/Z
search: v -> v min
search: from tag: 13 default vmin clk ^ clk_src clk crpr_pin null
search: to tag : 13 default vmin clk ^ clk_src clk crpr_pin null
search: 0.022 + 0.000 = 0.022 < MIA
search: buf1/Z
search: v -> v max
search: from tag: 15 default vmax clk ^ clk_src clk crpr_pin null
search: to tag : 15 default vmax clk ^ clk_src clk crpr_pin null
search: 0.022 + 0.000 = 0.022 > MIA
search: find arrivals inv1/ZN
search: inv1/A
search: ^ -> v min
search: from tag: 12 default ^min clk ^ clk_src clk crpr_pin null
search: to tag : 13 default vmin clk ^ clk_src clk crpr_pin null
search: 0.018 + 0.006 = 0.024 < MIA
search: inv1/A
search: ^ -> v max
search: from tag: 14 default ^max clk ^ clk_src clk crpr_pin null
search: to tag : 15 default vmax clk ^ clk_src clk crpr_pin null
search: 0.018 + 0.006 = 0.024 > MIA
search: inv1/A
search: v -> ^ min
search: from tag: 13 default vmin clk ^ clk_src clk crpr_pin null
search: to tag : 12 default ^min clk ^ clk_src clk crpr_pin null
search: 0.022 + 0.010 = 0.032 < MIA
search: inv1/A
search: v -> ^ max
search: from tag: 15 default vmax clk ^ clk_src clk crpr_pin null
search: to tag : 14 default ^max clk ^ clk_src clk crpr_pin null
search: 0.022 + 0.010 = 0.032 > MIA
search: find arrivals reg1/D
search: inv1/ZN
search: ^ -> ^ min
search: from tag: 12 default ^min clk ^ clk_src clk crpr_pin null
search: to tag : 12 default ^min clk ^ clk_src clk crpr_pin null
search: 0.032 + 0.000 = 0.032 < MIA
search: inv1/ZN
search: ^ -> ^ max
search: from tag: 14 default ^max clk ^ clk_src clk crpr_pin null
search: to tag : 14 default ^max clk ^ clk_src clk crpr_pin null
search: 0.032 + 0.000 = 0.032 > MIA
search: inv1/ZN
search: v -> v min
search: from tag: 13 default vmin clk ^ clk_src clk crpr_pin null
search: to tag : 13 default vmin clk ^ clk_src clk crpr_pin null
search: 0.024 + 0.000 = 0.024 < MIA
search: inv1/ZN
search: v -> v max
search: from tag: 15 default vmax clk ^ clk_src clk crpr_pin null
search: to tag : 15 default vmax clk ^ clk_src clk crpr_pin null
search: 0.024 + 0.000 = 0.024 > MIA
search: found 13 arrivals
search: find end slack reg1/D
search: find end slack reg1/QN
search: find end slack out1
Startpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Endpoint: out1 (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ reg1/CK (DFF_X1)
0.08 0.08 ^ reg1/Q (DFF_X1)
0.00 0.08 ^ out1 (out)
0.08 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.08 data arrival time
---------------------------------------------------------
9.92 slack (MET)
--- file path sanity ---
--- report_checks with rise/fall fields ---
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Slew Delay Time Description
-----------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.88 0.15 0.00 0.00 v in1 (in)
1.55 0.01 0.07 0.07 v buf1/Z (BUF_X1)
1.14 0.01 0.01 0.08 ^ inv1/ZN (INV_X1)
0.01 0.00 0.08 ^ reg1/D (DFF_X1)
0.08 data arrival time
0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
-----------------------------------------------------------------------
9.97 data required time
-0.08 data arrival time
-----------------------------------------------------------------------
9.89 slack (MET)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Cap Slew Delay Time Description
-----------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.97 0.20 0.00 0.00 ^ in1 (in)
0.20 0.00 0.00 ^ buf1/A (BUF_X1)
1.70 0.01 0.03 0.03 ^ buf1/Z (BUF_X1)
0.01 0.00 0.03 ^ inv1/A (INV_X1)
1.06 0.00 0.01 0.04 v inv1/ZN (INV_X1)
0.00 0.00 0.04 v reg1/D (DFF_X1)
0.04 data arrival time
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg1/CK (DFF_X1)
0.00 0.00 library hold time
0.00 data required time
-----------------------------------------------------------------------
0.00 data required time
-0.04 data arrival time
-----------------------------------------------------------------------
0.04 slack (MET)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Cap Slew Delay Time Description
-----------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.88 0.15 0.00 0.00 v in1 (in)
0.15 0.00 0.00 v buf1/A (BUF_X1)
1.55 0.01 0.07 0.07 v buf1/Z (BUF_X1)
0.01 0.00 0.07 v inv1/A (INV_X1)
1.14 0.01 0.01 0.08 ^ inv1/ZN (INV_X1)
0.01 0.00 0.08 ^ reg1/D (DFF_X1)
0.08 data arrival time
0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
-----------------------------------------------------------------------
9.97 data required time
-0.08 data arrival time
-----------------------------------------------------------------------
9.89 slack (MET)
--- set_load rise/fall ---
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in1 (in)
0.07 0.07 v buf1/Z (BUF_X1)
0.01 0.08 ^ inv1/ZN (INV_X1)
0.00 0.08 ^ reg1/D (DFF_X1)
0.08 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.08 data arrival time
---------------------------------------------------------
9.89 slack (MET)
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v in1 (in)
0.07 0.07 v buf1/Z (BUF_X1)
0.01 0.08 ^ inv1/ZN (INV_X1)
0.00 0.08 ^ reg1/D (DFF_X1)
0.08 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg1/CK (DFF_X1)
-0.03 9.97 library setup time
9.97 data required time
---------------------------------------------------------
9.97 data required time
-0.08 data arrival time
---------------------------------------------------------
9.89 slack (MET)
--- with_output_to_variable nesting ---
v1 captured 984 chars
v2 captured 1967 chars
--- redirect_string with reports ---
redirect string: 1414 chars
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