File size: 519 Bytes
f61bac1 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 | from openroad import Design, Tech
import helpers
import rcx_aux
tech = Tech()
tech.readLef("sky130hs/sky130hs.tlef")
design = helpers.make_design(tech)
rcx_aux.bench_wires(design, len=100, all=True)
def_file = helpers.make_result_file("generate_pattern.def")
verilog_file = helpers.make_result_file("generate_pattern.v")
rcx_aux.bench_verilog(design, filename=verilog_file)
design.writeDef(def_file)
helpers.diff_files("generate_pattern.defok", def_file)
helpers.diff_files("generate_pattern.vok", verilog_file)
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