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verilog_data-1

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verilog_data-1
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Header:
  version: "1.0"
  unit: "micron"
  precision: 2000
  include:
    - example.3dbv

Design:
  name: "TopDesign"

ChipletInst:
  soc_inst:
    reference: SoC
  soc_inst_duplicate:
    reference: SoC

Stack:
  soc_inst:
    loc: [100.0, 200.0]
    z: 0.0
    orient: R0
  soc_inst_duplicate:
    loc: [100.0, 200.0]
    z: 300.0
    orient: MZ

Connection:
  soc_to_soc:
    top: soc_inst_duplicate.regions.front_reg
    bot: soc_inst.regions.front_reg
    thickness: 0.0

Path:
  Path1:
    - soc_inst.regions.front_reg
    - NOT soc_inst_duplicate.regions.back_reg
    - soc_inst_duplicate.regions.front_reg
  Path2:
    - soc_inst.regions.back_reg
    - soc_inst_duplicate.regions.back_reg