File size: 787 Bytes
f61bac1 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 | Header:
version: "1.0"
unit: "micron"
precision: 2000
include:
- example.3dbv
Design:
name: "TopDesign"
external:
verilog_file: "top.v"
ChipletInst:
soc_inst:
reference: SoC
external:
verilog_file: "soc.v"
sdc_file: "/path/to/soc.sdc"
def_file: ../fake_macros.def
soc_inst_duplicate:
reference: SoC
external:
verilog_file: "soc.v"
sdc_file: "/path/to/soc.sdc"
Stack:
soc_inst:
loc: [100.0, 200.0]
z: 0.0
orient: R0
soc_inst_duplicate:
loc: [100.0, 200.0]
z: 300.0
orient: MZ
Connection:
soc_to_soc:
top: soc_inst_duplicate.regions.front_reg
bot: soc_inst.regions.front_reg
thickness: 0.0
soc_to_virtual:
top: soc_inst.regions.back_reg
bot: ~
thickness: 0.0
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