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verilog_data-1
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#!define NG45_PATH ../Nangate45

Header:
  version: 2.5
  unit: micron
  precision: 2000

ChipletDef:
  SoC:
    type: die
    design_area: [955, 1082]
    shrink: 1
    tsv: false
    thickness: 300
    offset: [0, 0]
    cad_layer:
      108;101:
        type: design_area
    regions:
      front_reg:
        side: front
        coords:
          - [0, 0]
          - [955, 0]
          - [955, 1082]
          - [0, 1082]
      back_reg:
        side: back
        coords:
          - [0, 0]
          - [955, 0]
          - [955, 1082]
          - [0, 1082]
        bmap: example.bmap
        pmap: Collateral/SoC/design/SoC_r1.pmap
        layer: metal1
    external:
      APR_tech_file: [NG45_PATH/*_tech.lef]
      liberty_file: [NG45_PATH/fake_macros.lib]
      LEF_file: [NG45_PATH/fake_macros.lef, NG45_PATH/fake_bumps.lef]