File size: 4,403 Bytes
f61bac1 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 | // SPDX-License-Identifier: BSD-3-Clause
// Copyright (c) 2026, The OpenROAD Authors
#include <string>
#include "gtest/gtest.h"
#include "odb/db.h"
#include "odb/dbWireCodec.h"
#include "tst/fixture.h"
namespace odb {
// Unit tests for dbBlock::designIsRouted(): a design is "routed" when every
// signal (non-special) net with more than one pin either has routing
// (wires/vias) or is connected by abutment. Special nets are ignored.
class TestDesignIsRouted : public tst::Fixture
{
protected:
void SetUp() override
{
loadTechAndLib(
"tech", "Nangate45.lef", "_main/test/Nangate45/Nangate45.lef");
dbChip* chip = dbChip::create(db_.get(), db_->getTech());
block_ = dbBlock::create(chip, "top");
}
// Create a 2-pin signal net connecting the output of one inverter to the
// input of another (pin_count == 2, so it must be routed to pass).
dbNet* makeMultiPinNet(const std::string& name)
{
dbNet* net = dbNet::create(block_, name.c_str());
dbMaster* inv = db_->findMaster("INV_X1");
dbInst* i0 = dbInst::create(block_, inv, (name + "_i0").c_str());
dbInst* i1 = dbInst::create(block_, inv, (name + "_i1").c_str());
i0->findITerm("ZN")->connect(net);
i1->findITerm("A")->connect(net);
return net;
}
// Attach a trivial metal1 wire so the net counts as routed.
void routeNet(dbNet* net)
{
dbTechLayer* metal1 = db_->getTech()->findLayer("metal1");
dbWire* wire = dbWire::create(net);
dbWireEncoder encoder;
encoder.begin(wire);
encoder.newPath(metal1, dbWireType::ROUTED);
encoder.addPoint(0, 0);
encoder.addPoint(0, 1000);
encoder.end();
}
dbBlock* block_;
};
// A design whose multi-pin signal net carries wires is fully routed.
TEST_F(TestDesignIsRouted, RoutedSignalNet)
{
dbNet* net = makeMultiPinNet("n1");
routeNet(net);
EXPECT_TRUE(block_->designIsRouted(/*verbose=*/false));
}
// Special (power/ground) nets are skipped entirely: an unrouted special net
// does not make the design unrouted.
TEST_F(TestDesignIsRouted, SpecialNetsAreIgnored)
{
dbNet* net = makeMultiPinNet("vdd");
net->setSpecial();
// Intentionally left unrouted.
EXPECT_TRUE(block_->designIsRouted(/*verbose=*/false));
}
// A mix of an (ignored) special net and a routed signal net is fully routed.
TEST_F(TestDesignIsRouted, MixedSpecialAndRoutedSignalNets)
{
dbNet* special = makeMultiPinNet("vdd");
special->setSpecial();
dbNet* signal = makeMultiPinNet("n1");
routeNet(signal);
EXPECT_TRUE(block_->designIsRouted(/*verbose=*/false));
}
// A net with a single pin needs no routing and never makes a design unrouted.
TEST_F(TestDesignIsRouted, SinglePinNetIsRouted)
{
dbNet* net = dbNet::create(block_, "n1");
dbInst* inst = dbInst::create(block_, db_->findMaster("INV_X1"), "i0");
inst->findITerm("A")->connect(net);
EXPECT_TRUE(block_->designIsRouted(/*verbose=*/false));
}
// A design with no nets is trivially routed.
TEST_F(TestDesignIsRouted, EmptyDesignIsRouted)
{
EXPECT_TRUE(block_->designIsRouted(/*verbose=*/false));
}
// A multi-pin signal net with no wires (and no abutment) is unrouted.
TEST_F(TestDesignIsRouted, UnroutedSignalNetFails)
{
makeMultiPinNet("n1");
EXPECT_FALSE(block_->designIsRouted(/*verbose=*/false));
}
// An unrouted signal net is detected even when ignored special nets coexist.
TEST_F(TestDesignIsRouted, UnroutedSignalNetWithSpecialNetsFails)
{
dbNet* special = makeMultiPinNet("vdd");
special->setSpecial();
makeMultiPinNet("n1"); // unrouted signal net
EXPECT_FALSE(block_->designIsRouted(/*verbose=*/false));
}
// Non-verbose mode reports an unrouted design without emitting any warning.
TEST_F(TestDesignIsRouted, NonVerboseEmitsNoWarning)
{
makeMultiPinNet("n1");
makeMultiPinNet("n2");
const int warnings_before = logger_.getWarningCount();
EXPECT_FALSE(block_->designIsRouted(/*verbose=*/false));
EXPECT_EQ(logger_.getWarningCount(), warnings_before);
}
// Verbose mode returns false and warns once per unrouted net (ODB-0232),
// scanning all nets rather than short-circuiting.
TEST_F(TestDesignIsRouted, VerboseWarnsForEachUnroutedNet)
{
makeMultiPinNet("n1");
makeMultiPinNet("n2");
const int warnings_before = logger_.getWarningCount();
EXPECT_FALSE(block_->designIsRouted(/*verbose=*/true));
EXPECT_EQ(logger_.getWarningCount(), warnings_before + 2);
}
} // namespace odb
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