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f61bac1 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 | // Reproducer for the dbReadVerilog deep-descendant modBTerm
// false-attach bug
module sub_with_clk (input clk, input d, output zo);
DFF_X1 u_ff (.CK(clk), .D(d), .Q(zo));
endmodule
module mid (
input clk,
input txclk,
input d,
output zo1,
output zo2
);
sub_with_clk \iclkdiv/gen_phases[0].iclk (.clk(clk),
.d(d),
.zo(zo1));
sub_with_clk \iclkdiv/gen_phases[1].iclk (.clk(txclk),
.d(d),
.zo(zo2));
endmodule
module top (
input clk_a,
input clk_b,
input d_in,
output out1,
output out2
);
mid u_mid (.clk(clk_a), .txclk(clk_b), .d(d_in), .zo1(out1), .zo2(out2));
endmodule
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