File size: 2,123 Bytes
f61bac1 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 | library (buslib) {
comment : "";
delay_model : table_lookup;
simulation : false;
capacitive_load_unit (1,pf);
leakage_power_unit : 1pW;
current_unit : "1A";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1V";
library_features(report_delay_calculation);
input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
slew_derate_from_library : 1.0;
slew_lower_threshold_pct_fall : 20;
slew_lower_threshold_pct_rise : 20;
slew_upper_threshold_pct_fall : 80;
slew_upper_threshold_pct_rise : 80;
default_fanout_load : 1.0;
default_inout_pin_cap : 0.0;
default_input_pin_cap : 0.0;
default_output_pin_cap : 0.0;
nom_process : 1.0;
nom_temperature : 125.00;
nom_voltage : 1.62;
operating_conditions(worst_case_industrial) {
process : 1.0;
temperature : 125.00;
voltage : 1.62;
tree_type : "worst_case_tree" ;
}
default_operating_conditions : worst_case_industrial ;
default_wire_load_mode : enclosed;
type (bus_3_0) {
base_type : array ;
data_type : bit ;
bit_width : 4;
bit_from : 3;
bit_to : 0;
}
cell (bus4) {
pin(clk) {
min_pulse_width_low : 0.600;
min_pulse_width_high : 0.600;
min_period : 0.500 ;
direction : input;
clock : true ;
capacitance : 0.0103 ;
}
bus (in) {
bus_type : bus_3_0;
direction : input ;
capacitance : 0.007700 ;
}
bus (out) {
bus_type : bus_3_0;
function : "in"
direction : output ;
timing () {
/* 1:1 timing arcs */
related_pin : "in" ;
timing_sense : "positive_unate" ;
cell_rise(scalar) {
values("1");
}
cell_fall(scalar) {
values("2");
}
rise_transition(scalar) {
values("1");
}
fall_transition(scalar) {
values("2");
}
}
}
}
}
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