File size: 1,558 Bytes
f61bac1 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 | // SPDX-License-Identifier: BSD-3-Clause
// Copyright (c) 2019-2025, The OpenROAD Authors
#pragma once
#include <string_view>
#include "db_sta/dbNetwork.hh"
#include "odb/db.h"
#include "sta/ConcreteLibrary.hh"
#include "sta/ConcreteNetwork.hh"
#include "sta/NetworkClass.hh"
#include "sta/VerilogReader.hh"
namespace utl {
class Logger;
}
namespace sta {
class dbSta;
class NetworkReader;
} // namespace sta
namespace ord {
class dbVerilogNetwork;
// Hierarchical network for read_verilog.
// Verilog cells and module networks are built here.
// It is NOT part of an Sta.
class dbVerilogNetwork : public sta::ConcreteNetwork
{
public:
dbVerilogNetwork(sta::dbSta* sta);
sta::Cell* findAnyCell(std::string_view name) override;
bool isBlackBox(sta::ConcreteCell* cell);
sta::dbNetwork* getDbNetwork()
{
return static_cast<sta::dbNetwork*>(db_network_);
}
private:
NetworkReader* db_network_ = nullptr;
};
void setDbNetworkLinkFunc(dbVerilogNetwork* network,
sta::VerilogReader* verilog_reader);
// Read a hierarchical Verilog netlist into a OpenSTA concrete network
// objects. The hierarchical network is elaborated/flattened by the
// link_design command and OpenDB objects are created from the flattened
// network.
bool dbLinkDesign(const char* top_cell_name,
dbVerilogNetwork* verilog_network,
odb::dbDatabase* db,
utl::Logger* logger,
bool hierarchy,
bool omit_filename_prop = false);
} // namespace ord
|