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784ee2c | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 | #SAMPLE INPUT FILE; VALUES NOT REALISTIC
{
# The process node.
"tech_nm": 7,
# The operating voltage.
"voltage": 0.7,
# String to add in front of every metal layer number for the layer name.
"metal_prefix": "M",
# Horizontal Metal layer for macro pins
"metal_layer": "M4",
# The pin width for signal pins.
"pin_width_nm": 24,
# The minimum pin pitch for signal pins
"pin_pitch_nm": 48,
# Metal track pitch
"metal_track_pitch_nm": 48,
# Manufacturing Grid
"manufacturing_grid_nm": 1,
# Contacted Poly Pitch
"contacted_poly_pitch_nm": 54,
#column mux factor
"column_mux_factor": 1,
# Fin pitch
"fin_pitch_nm" : 27,
# Optional snap the width and height of the sram to a multiple value.
"snap_width_nm": 190,
"snap_height_nm": 1400,
"memory_type": "RAM",
"port_configuration": "DP",
# List of SRAM configurations (name width depth and banks)
"srams": [
{"name": "dpsram_256x32", "width": 32, "depth": 256, "banks": 2},
{"name": "dpsram_256x32_h", "width": 32, "depth": 256, "banks": 2,
"additional_height": 7},
{"name": "dpsram_256x256", "width": 256, "depth": 256, "banks": 1}
]
}
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