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784ee2c | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 | // See LICENSE.SiFive for license details.
/** This black-boxes a Clock Divider by 3.
* The output clock is phase-aligned to the input clock.
* Do NOT use this in synthesis; the duty cycle is 2:1.
*
* Because Chisel does not support
* blocking assignments, it is impossible
* to create a deterministic divided clock.
*
* @param clk_out Divided Clock
* @param clk_in Clock Input
*
*/
module ClockDivider3 (output reg clk_out, input clk_in);
reg delay;
initial begin
clk_out = 1'b0;
delay = 1'b0;
end
always @(posedge clk_in) begin
if (clk_out == 1'b0) begin
clk_out = 1'b1;
delay <= 1'b0;
end else if (delay == 1'b1) begin
clk_out = 1'b0;
delay <= 1'b0;
end else begin
delay <= 1'b1;
end
end
endmodule // ClockDivider3
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