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README.md
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---
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language:
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- en
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license: mit
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task_categories:
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- text-generation
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tags:
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- assembly
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- security
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- constant-time
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- side-channels
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- binsec
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size_categories:
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- n<1K
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dataset_info:
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features:
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- name: task_name
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dtype: string
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- name: flag_x86_64
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dtype: string
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- name: flag_aarch64_linux
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dtype: string
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- name: flag_riscv
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dtype: string
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- name: x86_64
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dtype: string
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- name: aarch64_linux
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dtype: string
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- name: riscv
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dtype: string
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- name: test_c
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dtype: string
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splits:
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- name: test
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num_bytes: 765528
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num_examples: 10
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download_size: 119846
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dataset_size: 765528
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configs:
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- config_name: default
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data_files:
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- split: test
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path: data/test-*
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---
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# RelBench-O2: Constant-Time Assembly at -O2
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| Column | Description |
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|--------|-------------|
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| `task_name` | Sample identifier, e.g. `ct_select_1` |
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| `
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| `
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| `
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| `flag_riscv` | BinSec verdict for the RISC-V `-O2` build |
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| `x86_64` | x86-64 assembly at -O2 (**Intel syntax**, built with `-masm=intel`) |
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| `aarch64_linux` | AArch64 assembly at -O2 |
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| `riscv` | RISC-V RV64 (`rv64gc`/`lp64d`) assembly at -O2 |
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- **Total records**: 10
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|---|---|
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| `
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## The constant-time oracle
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**The verdict is per build.** The same program can be secure on one target and insecure on
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another, because the three backends make different branch/`cmov`/`csel` choices at -O2.
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## Usage
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record = ds[0]
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src_asm = record["x86_64"] # source-side assembly
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tgt_asm = record["riscv"] # reference target-side assembly
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leaky = record["flag_riscv"] == "insecure" #
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harness = record["test_c"] # rebuild + recheck a candidate against BinSec
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```
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---
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language:
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+
- en
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license: mit
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task_categories:
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- text-generation
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tags:
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- assembly
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- security
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- constant-time
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- side-channels
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- binsec
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size_categories:
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- n<1K
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---
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# RelBench-O2: Constant-Time Assembly at -O2
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| Column | Description |
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|--------|-------------|
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| `task_name` | Sample identifier, e.g. `ct_select_1` |
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| `flag_x86_64` | BinSec constant-time verdict for the x86-64 `-O2` build: `secure`, `insecure`, or `unknown` |
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| `flag_aarch64_linux` | Same, for the AArch64 `-O2` build |
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| `flag_riscv` | Same, for the RISC-V `-O2` build |
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| `x86_64` | x86-64 assembly at -O2 (**Intel syntax**, built with `-masm=intel`) |
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| `aarch64_linux` | AArch64 assembly at -O2 |
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| `riscv` | RISC-V RV64 (`rv64gc`/`lp64d`) assembly at -O2 |
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- **Total records**: 10
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| column | secure | insecure | unknown |
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|---|---|---|---|
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| `flag_x86_64` | 7 | 3 | 0 |
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| `flag_aarch64_linux` | 9 | 1 | 0 |
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| `flag_riscv` | 4 | 6 | 0 |
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## The constant-time oracle
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**The verdict is per build.** The same program can be secure on one target and insecure on
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another, because the three backends make different branch/`cmov`/`csel` choices at -O2.
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That is why the verdict is not collapsed into one label: each target carries its own
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`flag_*` column.
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## Usage
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record = ds[0]
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src_asm = record["x86_64"] # source-side assembly
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tgt_asm = record["riscv"] # reference target-side assembly
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leaky = record["flag_riscv"] == "insecure" # per-target verdict
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harness = record["test_c"] # rebuild + recheck a candidate against BinSec
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```
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