| ; MACROGROK — INFER4 (4-input fixed-point binary decision) | |
| ; AGC-inspired pseudo-ISA. Not authentic yaYUL. 15 data bits + parity. | |
| ; See README.md for Q formats and memory map. | |
| ; ===== FIXED / ROM ===== | |
| WEIGHTS_Q1_14: DC 2458, -1638, 819, 3277 ; Q1.14 | |
| BIAS_Q3_12: DC -256 ; Q3.12 | |
| ALPHA_Q1_14: DC 12288 ; 0.75 Q1.14 | |
| ONE_Q1_14: DC 16384 | |
| OUT_MIN_Q1_14: DC -16384 | |
| OUT_MAX_Q1_14: DC 16383 | |
| SCORE_MIN_Q3_12: DC -8192 | |
| SCORE_MAX_Q3_12: DC 8191 | |
| ; ===== ERASABLE / RAM ===== | |
| INPUT: DS 4 | |
| STATE: DS 1 | |
| OUTPUT: DS 1 | |
| ACC_HI: DS 1 | |
| ACC_LO: DS 1 | |
| PROD_HI: DS 1 | |
| PROD_LO: DS 1 | |
| TMP0: DS 1 | |
| TMP1: DS 1 | |
| FLAGS: DS 1 | |
| FLAG_VALID EQU 0001 | |
| FLAG_SAT EQU 0002 | |
| FLAG_POSITIVE EQU 0004 | |
| ; ===== PRIMITIVE MACROS ===== | |
| ; LOAD/STORE/ADD/SUB/MUL16/ADD32/ASR32/CMP/BR* assumed. | |
| MACRO CLR_ACC | |
| CLR ACC_HI | |
| CLR ACC_LO | |
| ENDM | |
| MACRO MAC_Q1_14 a, b | |
| LOAD R0, a | |
| LOAD R1, b | |
| MUL16 R0, R1 ; PROD_HI:PROD_LO | |
| LOAD R2, PROD_HI | |
| LOAD R3, PROD_LO | |
| ASR32 R2:R3, 4 | |
| ADD32 ACC_HI:ACC_LO, R2:R3 | |
| ENDM | |
| MACRO ACC_TO_Q3_12 dest | |
| ASR32 ACC_HI:ACC_LO, 12 | |
| STORE dest, ACC_LO | |
| ENDM | |
| MACRO SAT_Q3_12 value, lo, hi | |
| LOAD R0, value | |
| LOAD R1, lo | |
| CMP R0, R1 | |
| BRLT %%LOW | |
| LOAD R1, hi | |
| CMP R0, R1 | |
| BRGT %%HIGH | |
| BR %%DONE | |
| %%LOW: | |
| LOAD R0, lo | |
| STORE value, R0 | |
| LOAD R1, FLAGS | |
| OR R1, FLAG_SAT | |
| STORE FLAGS, R1 | |
| BR %%DONE | |
| %%HIGH: | |
| LOAD R0, hi | |
| STORE value, R0 | |
| LOAD R1, FLAGS | |
| OR R1, FLAG_SAT | |
| STORE FLAGS, R1 | |
| %%DONE: | |
| ENDM | |
| MACRO DOT4_Q1_14 | |
| CLR_ACC | |
| MAC_Q1_14 INPUT+0, WEIGHTS_Q1_14+0 | |
| MAC_Q1_14 INPUT+1, WEIGHTS_Q1_14+1 | |
| MAC_Q1_14 INPUT+2, WEIGHTS_Q1_14+2 | |
| MAC_Q1_14 INPUT+3, WEIGHTS_Q1_14+3 | |
| ENDM | |
| MACRO THRESHOLD_Q3_12 | |
| LOAD R0, TMP0 | |
| CLR R1 | |
| CMP R0, R1 | |
| BRLT %%NEG | |
| LOAD R0, ONE_Q1_14 | |
| STORE TMP1, R0 | |
| LOAD R0, FLAGS | |
| OR R0, FLAG_POSITIVE | |
| STORE FLAGS, R0 | |
| BR %%DONE | |
| %%NEG: | |
| LOAD R0, OUT_MIN_Q1_14 | |
| STORE TMP1, R0 | |
| %%DONE: | |
| ENDM | |
| MACRO UPDATE_STATE_3_4 | |
| LOAD R0, STATE | |
| ADD R1, R0 | |
| ADD R1, R0 | |
| ADD R1, R0 ; R1=3*STATE | |
| LOAD R2, TMP1 | |
| ADD R1, R2 ; 3*STATE+TARGET | |
| ASR R1, 2 ; /4 | |
| STORE STATE, R1 | |
| ENDM | |
| ; ===== MAIN ===== | |
| INFER4: | |
| CLR FLAGS | |
| DOT4_Q1_14 | |
| ACC_TO_Q3_12 TMP0 | |
| LOAD R0, TMP0 | |
| LOAD R1, BIAS_Q3_12 | |
| ADD R0, R1 | |
| STORE TMP0, R0 | |
| SAT_Q3_12 TMP0, SCORE_MIN_Q3_12, SCORE_MAX_Q3_12 | |
| THRESHOLD_Q3_12 | |
| UPDATE_STATE_3_4 | |
| LOAD R0, STATE | |
| STORE OUTPUT, R0 | |
| LOAD R0, FLAGS | |
| OR R0, FLAG_VALID | |
| STORE FLAGS, R0 | |
| RET | |